1. Field of the Invention
The present invention relates to a data driven type information processing apparatus. More specifically, the present invention relates to a data driven type information processing apparatus having such a function that erases at least one data packet on a circulation pipeline, and transfers another data packet on the circulation pipeline to a host.
2. Description of the Background Art
Along with recent development of multi-media applications, a large amount of operations are required in image processing, for example. A data driven type information processing apparatus (hereinafter referred to as a data driven type processor) has been proposed as an apparatus for processing such a large amount of operations at high speed. In a data driven type processor, a process proceeds in accordance with the rule that when input data necessary for executing a certain process are all prepared, and resources including an arithmetic processor necessary for that process are allocated, the process is executed.
A data processing apparatus including information processing operation of the data driven type uses a data transmitting apparatus employing asynchronous handshake method. In such a data transmitting apparatus, a plurality of data transmission paths are connected, and the data transmission paths transmit/receive data transmission request signals (hereinafter referred to as SEND signals) and transfer acknowledge signal (hereinafter referred to as ACK signals) indicating whether data transfer is permitted or not, with each other, whereby autonomous data transfer is performed.
FIG. 5 represents a data packet format applied to the prior art and to the present invention. Referring to FIG. 5, a data packet includes a destination node number field F1 storing a destination node number ND#; a generation number field F2 storing a generation number GN#; an instruction code field F3 storing an instruction code OPC; and a data field F4 storing data DATA. The generation number is a number for distinguishing data groups to be processed in parallel from each other. The destination node number is a number for distinguishing input data of the same generation from each other. The instruction code is for executing an instruction stored in an instruction decoder.
FIG. 6 is a block diagram showing a configuration of the data transmission path. The data transmission path includes a self-synchronous type transfer control circuit (hereinafter referred to as a C element) 3a, and a data holding circuit (hereinafter referred to as a pipeline register) 3b including a D type flip-flop. The C element 3a has a pulse input terminal CI receiving a pulse; a transfer acknowledge output terminal RO outputting a transfer acknowledge signal indicating permission or inhibition of transfer; a pulse output terminal CO outputting a pulse; a transfer acknowledge input terminal RI receiving the transfer acknowledge signal indicating permission or inhibition of transfer; and a pulse output terminal CP for providing a clock pulse controlling data holding operation of pipeline register 3b. 
FIGS. 7A to 7E are timing charts representing the operation of the C element shown in FIG. 6.
C element 3a receives a pulse shown in FIG. 7A from terminal CI, and when the input transfer acknowledging signal such as shown in FIG. 7E provided from terminal RI represents a transfer permitted state, it outputs a pulse shown in FIG. 7D from terminal CO, and outputs a pulse shown in FIG. 7C to pipeline register 3b. In response to the pulse applied from C element 3a, pipeline register 3b holds the applied input packet data, or provides the held data as an output packet data.
FIG. 8 is a block diagram showing the data transmission path shown in FIG. 6 connected sequentially through a prescribed logic circuit. Referring to FIG. 8, an input packet data is transferred in the order of pipeline registers 4a→4b→4c, while sequentially processed by logic circuits 6a and 6b. When pipeline register 4a is in a data holding state, for example, and the succeeding pipeline register 4b is in the data holding state, data is not transmitted from pipeline register 4a to pipeline register 4b. 
When the succeeding pipeline register 4b is in a state not holding data, or when it enters a state not holding data, the data is transmitted from pipeline register 4a, processed by logic circuit 6a and fed to pipeline register 4b with at least a preset delay time. Such a control in which data is transferred asynchronously with at least a preset delay time, in accordance with the SEND signal input/output at CI and CO terminals and ACK signals input/output at RI and RO terminals between adjacent connected pipeline registers is referred to as a self-synchronous transfer control, and a circuit controlling such a data transfer is referred to as a self-synchronous transfer control circuit.
FIG. 9 is a specific circuit diagram of the C element shown in FIG. 6. The C element is described, for example, in U.S. Pat. No. 5,373,204. Referring to FIG. 9, pulse input terminal CI receives a pulse-shaped SEND signal (transfer request signal) from a preceding stage, and a transfer acknowledge output terminal RO provides the ACK signal (transfer acknowledge signal) to the preceding stage. Pulse output terminal CO provides the pulse-shaped SEND signal to a succeeding stage, and the transfer acknowledge input terminal RI receives the ACK signal from the succeeding stage.
A master reset input terminal MR receives a master reset signal. When a pulse at the “H” (high) level is applied to master reset input terminal MR, it is inverted by an inverter 5F to the “L” (low) level, flip-flops 5a and 5b are reset, and the C element is initialized. Pulse output terminal CO and transfer acknowledge output terminal RO both output the “H” level signals as the initial state. That the output of transfer acknowledge output terminal RO is at the “H” level indicates the transfer permitted state, whereas the output being at the “L” level indicates a transfer inhibited state. The output of pulse output terminal CO being the “H” level represents a state in which data transfer from the succeeding stage is not requested, while the output being at the “L” level represents a state in which data transfer is requested or data is being transferred from the succeeding stage.
When the “L” level signal is input to pulse input terminal CI, that is, when a data transfer request is issued from the preceding stage, flip-flop 5a is set, and provides the “H” level signal at its output Q. The “H” level signal is inverted by inverter 5g, whereby the “L” level signal is output from transfer acknowledge input terminal RO, inhibiting further data transfer.
After a prescribed time period, the “H” level signal is input to pulse input terminal CI, and data set from the preceding stage to the C element is completed. When, in this state, the “H” level signal is input from transfer acknowledge input terminal RI, that is, data transfer is permitted by the succeeding stage, and in addition, the “H” level signal is output from pulse output terminal CO, that is, when data is not being transferred to the succeeding stage (data transfer request is not issued to the succeeding stage), then NAND gate 5c is rendered active, providing the “L” level signal.
As a result, flip-flops 5a and 5b are both reset, and flip-flop 5b provides the “H” level signal from pulse output terminal CP to the pipeline register through a delay element 5e, and provides the SEND signal at the “L” level from pulse output terminal CO to the C element of the succeeding stage through a delay element 5d. More specifically, data transfer request is issued to the succeeding stage. The C element of the succeeding stage, receiving the SEND signal at the “L” level, outputs the ACK signal set to the “L” level, representing transfer inhibition, from the RO terminal, so as to prevent further data transfer to the C element.
The C element receives the ACK signal at the “L” level from the transfer acknowledge input terminal RI, and by this signal, flip-flop 4b is set. As a result, the “L” level signal is output from pulse output terminal CP to the pipeline register through delay element 5e, and the SEND signal at the “H” level is output from the pulse output terminal CO to the succeeding stage through delay element 5d, and thus data transfer is completed.
FIG. 10 is a schematic block diagram of a conventional data driven type information processing apparatus implemented including the data transfer path shown in FIG. 8. Referring to FIG. 10, the data driven type information processing apparatus Pe includes a junction unit JNC, a firing control unit FC, a processing unit FP, a program storing unit PS, a branching unit BRN, a plurality of pipeline registers 4a to 4c and a plurality of C elements 2a to 2c. Respective C elements 2a to 2c control packet transfer with the corresponding processing units (FC, FP, PS) by exchanging packet transfer pulses (signals at CI, CO, RI and RO) between the C elements of the preceding and succeeding stages. Respective pipeline registers 4a to 4c take in and hold data input from the processing unit of the preceding stage in response to the pulse inputs from corresponding C elements 2a to 2c, feed the data to the output stage, and hold the data until the next pulse is input.
Referring to FIG. 10, when the data packet shown in FIG. 5 is input to the processor Pe, the input packet is first passed through junction unit JNC, transmitted to firing control unit FC, and a data pair is formed between packets having the same destination node number and the same generation number. More specifically, two different data packets having identical node number and the generation number are detected, and of these two having the same numbers, one data packet is additionally stored in the data field F4 (FIG. 5) of the other data packet, and the resulting data packet is output. The data packet storing the data pair (a set of data) in the data field F4 is then transmitted to operating unit FP. The operating unit FP receives the transmitted data packet as an input, based on the instruction code OPC of the input packet, performs a prescribed operation on the contents of the input packet, and stores the result of operation in the data field F4 of the input packet. Thereafter, the input packet is transmitted to program storing unit PS.
The program storing unit receives as an input the transmitted data packet, and reads, based on the destination node number ND# of the input packet, the node information (node number ND#) to which the packet should go, instruction information (instruction code OPC) to be executed next, and a copy flag CPY, from the program memory of the program storing unit PS. The read destination node number ND# and the instruction code OPC are stored in the destination node number field F1 and the instruction code field F3 of the input packet, respectively. Further, when the read copy flag CPY is “1”, the next address of the program memory is also determined to be valid, and a packet is generated which stores the destination node number ND# and the instruction code OPC that are stored at the next address.
The packet output from the program storing unit PS is transmitted to branching unit BRN and output or returned again to the processor, based on the destination node number ND#.
In a data driven type information processing apparatus, because of a lag in the order of arrival of data packets or because of dependency between data, a dead-lock state sometimes occurs, hindering execution of all subsequent operations. This phenomenon will be described with reference to FIG. 11. Assume, for example, that n packets (memory packet 1-memory packet n) are stored in the memory of firing control unit FC shown in FIG. 10, and there is no empty field. When a data packet 1 shown in FIG. 11 is input to firing control unit FC, the destination node number and the generation number of the tab held by the packet are compared with the destination node number and the generation number of a tag of a packet that has been stored in the internal memory. When arrival of a counterpart data packet 2 having the same tag is delayed and the counterpart packet cannot be detected, the data packet 1 is not stored in the memory as there is no empty space in the internal memory but directly output to a circulation pipeline. When the data packet 2 is input to the firing control unit FC thereafter, data packet 1 cannot be detected, and therefore, this data packet is also output directly to the circulation pipeline. In order that the data packet 1 or data packet 2 is stored in the memory in the firing control unit FC, it is necessary that any of the data packets stored in the memory of firing control unit FC has a tag matching the tag of any packet on the circulation pipeline and there is an empty space in the memory, making an empty space in the memory in the firing control unit FC.
When the data dependency of the program is as shown in FIG. 11, however, the data packet 1 is directly output to the circulation pipeline at first and data packet 2 input subsequently is also output to the circulation pipeline without firing and without executing any instruction, when there is no empty space in the memory in the firing control unit FC and the data packets 1 and 2 are input at different timings.
After the data packets 1 and 2 are circulated through the circulation pipeline and arrive the firing control unit FC, the situation is the same. Therefore, the n memory packets stored in the memory are all kept permanently un-fired, and therefore the memory is kept full.
When new data packets are input from the junction unit JNC and added to the circulating data packets, eventually, transfer from a pipeline to another pipeline becomes impossible, resulting in the dead-lock state.
When the dead-lock state occurs and subsequent execution is completely hindered, or at the start of executing a program, it is necessary to initialize the data driven type information processing apparatus PE. For this purpose, a pulse at the “H” level is applied to the master reset input terminal MR of the self-synchronous transfer control circuit shown in FIG. 8, so as to initialize all the C elements 2a to 2e and the data driven type information processing apparatus PE.
Thus, pulse output terminal CO and transfer acknowledge output terminal RO are both set to the initial state, providing the “H” level signals notifying that it is the transfer permitted state to the preceding stage and not requesting data transfer from the succeeding stage. Therefore, the data held by the pipeline register at the time of master reset is not transmitted to the pipeline register of the succeeding stage, and the data packet is overwritten by the data transmitted from the pipeline register of the preceding stage and eliminated. Thus, the data packets in all the pipeline registers are eliminated.
As described above, when the circulation pipeline comes to be dead-lock, preventing execution of all the subsequent operations, initialization is possible by a master reset input. As the circulation pipeline circulates returning from the branching unit BRN to the junction unit JNC as shown in FIG. 10, it has been difficult to find the cause of the dead-lock, even when the data packets on the circulation pipeline are all erased.